My Projects

DVLSI Project: ASIC design of a neural network

Project Overview Objective: To design a 3-layer neural network for image classification, design the architecture, and take it from the RTL stage to the GDSII layout. Tools: Cadence EDA suite (Genus, Innovus, Tempus, Voltus, etc.). Key Deliverables: RTL simulation and verification. Gate-level synthesis (GLS). Physical design and timing closure. Power analysis and optimization. Final GDSII file for fabrication.

About Program

The PG Level Advanced Certification Programme in VLSI Chip Design enables professionals to build VLSI chip designing capabilities that can power new-age technologies like AI, IoT, VR, Mobility, Cloud, and Analytics. The Department of Electronic Systems Engineering, IISc, with its pioneering and ongoing research and training in VLSI chip design, is best positioned to offer this programme. The programme is ideal for VLSI industry professionals who want to leverage expertise of modern tools and technologies.